Altera Corporation

Brent Alan Fairbanks

Francis B Heile

David Wolk Mendel

Bruce B Pedersen

David Karchmer

Ning Xue

Alan Louis Herrmann

Xiangyong Wang

Tamlyn V Rawls

XiangDong Tan

Methods and structures are disclosed for aligning high speed data across a plurality of lanes. In one embodiment, a method and integrated circuit ('IC') is provided for receiving and aligning scrambled training data across a plurality of data lanes before the data is descrambled. In some implementations, a known scrambled training pattern is different in each lane and alignment includes comparing incoming training data in each lane to different known scrambled training patterns in each lane. In some implementations, after scrambled data is aligned and then descrambled, it is checked against a known unscrambled training pattern to make sure that alignment of the scrambled training data was correct. In an alternative embodiment, data is descrambled before being aligned, but deskew circuitry output is monitored to determine if a training pattern ends at the same time across the plurality of lanes being aligned. If not, then data in a lane for which the training pattern ends earliest is delayed by an amount corresponding to the length of one or more cycles of the training pattern.

Deskew across high speed data lanes

A technique for checking a logic design for compliance with a set of design rules in a computer-aided logic design system. An initial logic design is provided in computer-readable form in a logic design file. A set of design rules expressing permitted and prohibited structural and functional logic device relationships is provided as a portion of a logic design simulation system capable of synthesizing the initial design into a simulated network list. The initial design is checked against the various design rules incorporated into the set, and any violation of the design rules by the initial logic design is visibly displayed to the user. In one mode of operation, a list of user selectable optional rules is visibly displayed. A hierarchy of levels of design compliance is also displayed for user selection. For some design rules, a comparison can be made with the synthesized version of the initial logic design in order to spot design rule violations introduced by the synthesis process.

Design verification method for programmable logic design

A method and associated computer program product is provided for determining placement of I/O pins on an integrated circuit device. In an exemplary embodiment, a set of pins to be placed is partitioned into pin groups prior to placing individual pins. After partitioning the pins into pin groups, pin groups may, in a preferred embodiment, be ranked according to difficulty of placement. Pins in the most difficult group are placed first by applying a method that, in a preferred embodiment, places pins within the limits imposed by current density requirements while achieving high pin density within those limits when pad resources are relatively limited.

I/O pin placement for a programmable logic device

A work group computing system for facilitating programmable logic device design among multiple engineers has a global work space including design project source files, a compilation basis, a compilation report text file, a binary assignments database and a user-readable assignments text file. Any number of local work spaces contain downloaded versions of any of the project source files, local compilation processing results for that user and a local assignment database containing records of downloaded assignments. Downloaded project source files or assignments are assigned states by the user such as default, locked, owned-write, owned-read only to facilitate coordination amongst the user engineers. The system controls editing of files so that two engineers may not inadvertently edit the same global source file at the same time. Individual engineers receive automatic updates of new versions of source files; files that are being edited are locked, and an isolation mode allows an engineer to work with source files in an unchanging state. Each engineer incrementally compiles local changes made to source files in his own user work space to produce a local set of compilation and processing results. Incremental compilation uses unedited source files, the basis from the global work space, and the user's edited local files to produce the local processing results. Upon satisfactory results, edited source files and local processing results may replace and overwrite global files and results. Multiple engineers are allowed to work on complex logic design that can be implemented on a single, large capacity device.

Incremental compilation of electronic design for work group

A programmable logic device (10) has a number of programmable logic elements (LES) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). An LAB incorporates one or more wide-input AND gates (74) for selectively combining the outputs of any number of LEs and producing a signal that is a logical combination of any number of its LEs. In variations of the invention, input signals may be selectively coupled to an AND gate by means of an OR gate (78) and may be selectively inverted by means of an XOR gate (76). A digital information processing system (500) incorporating the invention is disclosed. Various circuit techniques are provided for efficient implementation of a fast and wide exclusive OR or exclusive NOR function. A logic array block is equipped with a dedicated exclusive OR circuit with programmable inputs connected to selected terms from various logic cells, or outputs of the various logic cells. Another embodiment allows creating an embedded chain of exclusive OR gates to implement a wide exclusive OR gate by cascading a smaller exclusive OR gate within several logic cells.

Wide exclusive or and wide-input and for PLDS

A technique for allowing local compilation at any level within a design hierarchy tree for a programmable logic device allows a user to compile within the context of the entire design using inherited parameter values and assignments from any parent nodes within the design hierarchy tree. A user is allowed to perform an isolated, local compilation that gives a compilation result as if the lower level node had been compiled within the context of the complete design. This local compilation is performed even though assignments, parameters, and logic options of parent nodes have not been compiled. An 'action point' is specified at a node where a local compilation, timing analysis or simulation is to occur. A method compiles design source files that represent a PLD design. The design source files specify design entities that are represented as nodes in a design hierarchy tree. A first step analyzes the design source files to determine what design entities are represented in the source files. Starting from the root node down to the action point, the following steps are performed at each node: resolving current assignments based upon higher assignments at nodes located between the current node and the root node of said hierarchy tree, and elaborating the current node to produce a netlist. Once the action point node has been reached, then lower nodes of the hierarchy tree below the action point are elaborated down to the leaf nodes to produce a netlist for each of these lower nodes.

Growing community of inventors

Santa Clara, CA, United States of America

Brent Alan Fairbanks