Deskew across high speed data lanes

Abstract

Methods and structures are disclosed for aligning high speed data across a plurality of lanes. In one embodiment, a method and integrated circuit ('IC') is provided for receiving and aligning scrambled training data across a plurality of data lanes before the data is descrambled. In some implementations, a known scrambled training pattern is different in each lane and alignment includes comparing incoming training data in each lane to different known scrambled training patterns in each lane. In some implementations, after scrambled data is aligned and then descrambled, it is checked against a known unscrambled training pattern to make sure that alignment of the scrambled training data was correct. In an alternative embodiment, data is descrambled before being aligned, but deskew circuitry output is monitored to determine if a training pattern ends at the same time across the plurality of lanes being aligned. If not, then data in a lane for which the training pattern ends earliest is delayed by an amount corresponding to the length of one or more cycles of the training pattern.