Bradley Donald Herrman

This inventor holds 19 USPTO granted patents, primarily in Printed Circuit Boards. Top assignees: International Business Machines Corporation, Lenovo (Singapore) Pte. Ltd.. Active years: 1983-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Bradley Donald Herrman. Retrieved from https://idiyas.com/inventor/bradley-donald-herrman

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 19

% Patents Active = 73.7

Average Co-Inventor Count = 4.5

ph-index = 3

Forward Citations = 52(Granted Patents)

Location History:

Pompano Beach, FL (US) (1983)
Williston, VT (US) (1988)
Durham, NC (US) (2012)
Cary, NC (US) (2008 - 2018)

Company Filing History:

15 out of 166,351

International Business Machines Corporation

patents

4 out of 4,442

Lenovo (Singapore) Pte. Ltd.

patents

Years Active: 1983-2018

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Areas of Expertise:

Impedance Control

Dielectric Loss

Noise Coupling

Crosstalk Effects

High Speed Digital Systems

PCB Design

Component Testing

Dynamic Phase Equalization

Electrical Qualification

Bidirectional Transfer

Drive Strength Assessments

Column Redundancy

19 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10045434 - Reducing impedance discontinuities on a printed circuit board ('PCB') (2018-08-07),

2. 9390048 - Controlling characteristic impedance of a trace in a printed circuit board to compensate for external component loading (2016-07-12),

3. 9338881 - Manufacturing a printed circuit board with reduced dielectric loss (2016-05-10),

4. 9244120 - Simulation of printed circuit board impedance variations and crosstalk effects (2016-01-26),

5. 8390393 - Pre-distortion based impedence discontinuity remediation for via stubs and connectors in printed circuit board design (2013-03-05),

6. 8319113 - Printed circuit board with reduced dielectric loss (2012-11-27),

7. 8289101 - Pre-distortion based impedence discontinuity remediation for via stubs and connectors in printed circuit board design (2012-10-16),

8. 8289043 - Simulation of printed circuit board impedance variations and crosstalk effects (2012-10-16),

9. 8106666 - Testing an electrical component (2012-01-31),

10. 8084692 - Reducing noise coupling in high speed digital systems (2011-12-27),

11. 7956688 - Common mode cancellation in differential networks (2011-06-07),

12. 7813447 - Apparatus, system, and method for dynamic phase equalization in a communication channel (2010-10-12),

13. 7725783 - Method and apparatus for repeatable drive strength assessments of high speed memory DIMMs (2010-05-25),

14. 7701222 - Method for validating printed circuit board materials for high speed applications (2010-04-20),

15. 7533458 - Method for reducing noise coupling in high speed digital systems (2009-05-19),

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Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]