Aveek Sarkar is a notable inventor based in Mountain View, CA (US). He has made significant contributions to the field of circuit design and analysis, holding a total of 4 patents. His work primarily focuses on improving the accuracy of timing predictions and capacitance estimations in electronic circuits.

Latest Patents

Aveek Sarkar's latest patents include a method and software for predicting the timing delay of a circuit path using two different timing models. This innovative approach models the circuit path with two distinct timing models, allowing for the generation of a correction factor based on the variation between the timing responses. This correction factor is then applied to produce a more accurate timing prediction for the modeled circuit path. Another significant patent involves estimating capacitances using information extracted from a netlist. This process aggregates feature sizes of circuit devices connected to inputs and outputs, enabling a more precise determination of total capacitance, which is crucial for timing analysis.

Career Highlights

Aveek Sarkar is currently employed at Sun Microsystems, Inc., where he continues to develop cutting-edge technologies in circuit design. His expertise in timing analysis and capacitance estimation has positioned him as a valuable asset in the tech industry.

Collaborations

Throughout his career, Aveek has collaborated with notable colleagues, including Peter F Lai and Rambabu Pyapali. These collaborations have further enhanced his innovative contributions to the field.

Conclusion

Aveek Sarkar's work in circuit timing and capacitance estimation showcases his dedication to advancing technology in electronic design. His patents reflect a commitment to improving the accuracy and efficiency of circuit analysis, making him a prominent figure in the field.