The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2006
Filed:
Sep. 08, 2003
Aveek Sarkar, Mountain View, CA (US);
Yongning Sheng, Sunnyvale, CA (US);
Peter F. Lai, San Jose, CA (US);
Rambabu Pyapali, Cupertino, CA (US);
Aveek Sarkar, Mountain View, CA (US);
Yongning Sheng, Sunnyvale, CA (US);
Peter F. Lai, San Jose, CA (US);
Rambabu Pyapali, Cupertino, CA (US);
Sun Microsystems, Inc., Santa Clara, CA (US);
Abstract
The capacitances of one or more inputs/outputs of a circuit are estimated by using an extraction tool () to extract information associated with the inputs/outputs from a netlist. The information includes information associated with circuit devices directly connected to the inputs/outputs, particularly information related to device connectivity and the feature sizes of the device. Once the information is extracted, a capacitance determination element () aggregates the feature sizes of all the circuit devices connected to each respective input or output, to obtain aggregate feature sizes for each respective input/output. The aggregate feature size is used in determining the total capacitance of the input/output. The total capacitance thus determined can be provided to a timing analysis tool (), which uses the total capacitance of each input or output to generate a timing model for the circuit.