The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2005
Filed:
Mar. 24, 2003
Shyam Sundar, Sunnyvale, CA (US);
Aveek Sarkar, Mountain View, CA (US);
Peter F. Lai, San Jose, CA (US);
Rambabu Pyapali, Cupertino, CA (US);
Teong Ming Cheah, Sunnyvale, CA (US);
Shyam Sundar, Sunnyvale, CA (US);
Aveek Sarkar, Mountain View, CA (US);
Peter F. Lai, San Jose, CA (US);
Rambabu Pyapali, Cupertino, CA (US);
Teong Ming Cheah, Sunnyvale, CA (US);
Sun Microsystems, Inc., Santa Clara, CA (US);
Abstract
The present application describes various embodiments of a method and an apparatus for determining electromigration risks for signal nets in integrated circuits. A model for each one of the global nets connecting various circuit blocks in an integrated circuit is created using circuit blocks' timing model and detailed standard parasitic format representation (DSPF) of each global net. The final layout of the integrated circuit is not necessary to determine the electromigration risks. The models can be generated during the early stages of the design cycle once the DSPF of the global nets is available.