Chandler, AZ, United States of America

Ashish Gupta

This inventor holds 38 USPTO granted patents and 12 published patent applications and 1 EPO patent, primarily in High Performance Interconnect. Top assignees: Intel Corporation, Hewlett-Packard Development Company, L.p., Altera Corporation. Active years: 2003-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ashish Gupta. Retrieved from https://idiyas.com/inventor/ashish-gupta-6nvdyssg

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 38 

% Patents Active = 65.8

 

Average Co-Inventor Count = 4.2

ph-index = 8

Forward Citations = 220(Granted Patents)


Location History:

  • Cupertino, CA (US) (2003 - 2006)
  • San Jose, CA (US) (2004 - 2021)
  • Chandler, AZ (US) (2010 - 2023)

Company Filing History:


Years Active: 2003-2026

Loading Chart...
Loading Chart...
Areas of Expertise:
Network-On-Chip
User Recommendations
Thermal Management
Interconnects
Copper Nanorod
Heat Transfer
Memory Migration
Liquid TIM
Micro-Network
Debug Port
Synchronized Serial Interface
Virtualization
38 patents (USPTO):Explore Patents

Title: Innovations and Contributions of Ashish Gupta in the Field of High-Performance Interconnects

Introduction

Ashish Gupta is a notable inventor located in Chandler, AZ, recognized for his substantial contributions to the field of high-performance interconnects. With an impressive portfolio of 33 patents, Gupta has played a pivotal role in advancing technology within the semiconductor industry.

Latest Patents

Among his latest patents, Gupta has developed a high-performance interconnect apparatus featuring a physical layer (PHY) coupled to a serial, differential link consisting of multiple lanes. This innovative PHY integrates a transmitter and a receiver for each lane, with the transmitter designed to embed a clock along with data for transmission. Notably, the PHY periodically issues a blocking link state (BLS) request, which prompts an agent to enter a BLS, thus halting link layer flit transmission for a specified duration. During this time, the PHY harnesses the serial, differential link for various tasks, including in-band resets, transitions to low power states, and partial width state entries. This innovation significantly enhances the efficiency and performance of data transmission processes.

Career Highlights

Gupta has built a solid career working with prominent companies in the tech industry. He has contributed his expertise at Intel Corporation and Hewlett-Packard Development Company, L.P., where he has been involved in cutting-edge projects focusing on high-performance computing and interconnection technologies. His work has undoubtedly impacted the advancement of digital communications.

Collaborations

Throughout his career, Ashish Gupta has collaborated with several esteemed professionals, including Darren S. Jue and Venkatraman Iyer. These collaborations have fostered an environment of innovation and have led to significant breakthroughs in the development of advanced communication technologies.

Conclusion

In summary, Ashish Gupta stands out as an influential inventor in the realm of high-performance interconnects. His extensive patent portfolio and contributions to leading technology firms highlight his dedication to innovation and efficacy in enhancing data transmission capabilities. As technology continues to evolve, Gupta's work is expected to play an integral role in shaping the future of semiconductor and communication technologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…