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For the Inventor, By the Inventor

Dallas, TX, United States of America

Artur P Balasinski

This inventor holds 14 USPTO granted patents. Top assignees: Stmicroelectronics Gmbh, Sgs-Thomson Microelectronics Limited, Cypress Semiconductor Corporation. Active years: 1997-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Artur P Balasinski. Retrieved from https://idiyas.com/inventor/artur-p-balasinski

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 14

% Patents Active = 92.9

Average Co-Inventor Count = 2.4

ph-index = 8

Forward Citations = 200(Granted Patents)


Location History:

  • Scottsdale, AZ (US) (1998 - 1999)
  • Dallas, TX (US) (1997 - 2000)
  • Cupertino, CA (US) (2003 - 2010)

Company Filing History:

goldMedal6 out of 2,891 
 
Stmicroelectronics Gmbh
 patents
silverMedal4 out of 816 
 
Sgs-Thomson Microelectronics Limited
 patents
bronzeMedal2 out of 3,596 
 
Cypress Semiconductor Corporation
 patents
4. 2 out of 834,513 
Other
 patents

Years Active: 1997-2010

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14 patents (USPTO):Explore Patents
1. RE41068 - Spacer-type thin-film polysilicon transistor for low-power memory devices (2010-01-04),
2. 7231374 - Scheme for evaluating costs and/or benefits of manufacturing technologies (2007-06-12),
3. 7197737 - Techniques for placing dummy features in an integrated circuit based on dielectric pattern density (2007-03-27),
4. 6681376 - Integrated scheme for semiconductor device verification (2004-01-20),
5. 6562638 - Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout (2003-05-13),
6. 6093963 - Dual landing pad structure including dielectric pocket (2000-07-25),
7. 5960311 - Method for forming controlled voids in interlevel dielectric (1999-09-28),
8. 5945738 - Dual landing pad structure in an integrated circuit (1999-08-31),
9. 5909636 - Method of forming a landing pad structure in an integrated circuit (1999-06-01),
10. 5847464 - Method for forming controlled voids in interlevel dielectric (1998-12-08),
11. 5804472 - Method of making spacer-type thin-film polysilicon transistor for (1998-09-08),
12. 5795800 - Integrated circuit fabrication method with buried oxide isolation (1998-08-18),
13. 5705427 - Method of forming a landing pad structure in an integrated circuit (1998-01-06),
14. 5640023 - Spacer-type thin-film polysilicon transistor for low-power memory devices (1997-06-17),

Title: The Inventor Artur P Balasinski: Pioneering Innovations in Dallas

Introduction: Artur P Balasinski is a visionary inventor based in Dallas, Texas, known for his groundbreaking contributions to various industries through his innovative creations.

Latest Patents: Artur P Balasinski holds several patents in the fields of technology, healthcare, and consumer products, showcasing his diverse range of expertise and creativity.

Career Highlights: With a career spanning over two decades, Artur has consistently pushed the boundaries of what is possible, revolutionizing the way we interact with technology and improving the quality of life for many.

Collaborations: Throughout his career, Artur P Balasinski has collaborated with leading companies, research institutions, and universities to bring his inventions to life, demonstrating his ability to work across disciplines and industries.

Conclusion: Artur P Balasinski's passion for innovation and his relentless drive to create a better future make him a true pioneer in the world of inventions, leaving a lasting impact on society.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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