The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 1998
Filed:
Jul. 25, 1996
Applicant:
Inventors:
Tsiu Chiu Chan, Carrollton, TX (US);
Artur P Balasinski, Dallas, TX (US);
Assignee:
SGS-Thomson Microelectronics, Inc., Carrollton, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438149 ; 438199 ; 438238 ; 438520 ; 438526 ;
Abstract
A CMOS SRAM cell in which a patterned SIMOX layer forms a buried oxide beneath the PMOS devices, but not beneath the NMOS devices. Latchup is impossible, and well diffusions are not needed.
Chan, Tsiu. (1998). Integrated circuit fabrication method with buried oxide isolation (U.S. Patent No. 5795800). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5795800
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile