Wellesley, MA, United States of America

Arthur R Calawa

This inventor holds 5 USPTO granted patents. Top assignees: Massachusetts Institute of Technology, Other. Active years: 1982-1995.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Arthur R Calawa. Retrieved from https://idiyas.com/inventor/arthur-r-calawa

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 4.2

ph-index = 5

Forward Citations = 62(Granted Patents)


Location History:

  • Chelmsford, MA (US) (1982)
  • Wellesley, MA (US) (1990 - 1995)

Company Filing History:


Years Active: 1982-1995

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5 patents (USPTO):Explore Patents

Title: Arthur R. Calawa: Innovator in III-V Semiconductor Technology

Introduction

Arthur R. Calawa is a prominent inventor based in Wellesley, MA (US), known for his significant contributions to the field of III-V semiconductor technology. He holds a total of 5 patents, showcasing his innovative approach to integrated circuits and photoconductive devices.

Latest Patents

Calawa's latest patents include advancements in III-V based integrated circuits featuring low temperature growth buffers. One notable patent describes a new III-V buffer or passivation material produced by low temperature growth (LTG) of III-V compounds. This material exhibits unique properties that are particularly beneficial for closely spaced, submicron gate length active III-V semiconductor FET devices, such as HEMTs, MESFETs, and MISFETs. The LTG material is grown under ambient conditions, incorporating an excess of the more volatile III-V species, resulting in a crystalline, highly resistive material that is relatively insensitive to light. This material can be overgrown with high-quality III-V active layers or used as a passivation material to insulate and protect active device structures. Another patent focuses on ultra-high-speed photoconductive devices utilizing semi-insulating layers. This device comprises a homoepitaxial semi-insulating III-V layer, produced by low temperature growth of III-V compounds through molecular beam epitaxy (MBE). In a GaAs embodiment, the layer is grown under arsenic stable growth conditions at substrate temperatures ranging from 150°C to about 300°C.

Career Highlights

Throughout his career, Calawa has worked with prestigious institutions, including the Massachusetts Institute of Technology. His work has significantly impacted the development of semiconductor technologies, particularly in enhancing the performance of photoconductive devices and integrated circuits.

Collaborations

Calawa has collaborated with notable individuals in the field, including Frank W. Smith and Michael J. Manfra. These collaborations have contributed to the advancement of semiconductor research and innovation.

Conclusion

Arthur R. Calawa's contributions to III-V semiconductor technology and his innovative patents highlight his role as a leading inventor in the field. His work continues to influence advancements in integrated circuits and photoconductive devices, showcasing the importance of innovation in technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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