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San Jose, CA, United States of America

Ankush Sood

USPTO Granted Patents = 6

Average Co-Inventor Count = 1.9

ph-index = 5

Forward Citations = 315(Granted Patents)

Location History:

Haryana, IN (2010)
San Jose, CA (US) (2014 - 2016)

Company Filing History:

Cadence Design Systems, Inc.

Years Active: 2010-2016

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6 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9411912 - Clock topology planning for reduced power consumption (2016-08-09),

2. 9280614 - Methods, systems, and apparatus for clock topology planning with reduced power consumption (2016-03-08),

3. 9135375 - Methods for construction and optimization of a clock tree plan for reduced power consumption (2015-09-15),

4. 8826211 - Graphical user interface for physically aware clock tree planning (2014-09-02),

5. 8782591 - Physically aware logic synthesis of integrated circuit designs (2014-07-15),

6. 7774735 - Integrated circuit netlist migration (2010-08-10),

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