The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2014
Filed:
Dec. 31, 2012
Cadence Design Systems, Inc., San Jose, CA (US);
Tsuwei Ku, Cupertino, CA (US);
David Seibert, Mountain View, CA (US);
Huey-Yih Wang, Cupertino, CA (US);
Hua Song, Saratoga, CA (US);
Kai Zhu, Palo Alto, CA (US);
Yu-Fang Chung, Cupertino, CA (US);
Ankush Sood, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
In one embodiment of the invention, a method of synthesizing physical gates from register transfer logic code for an integrated circuit design is disclosed. The method includes reading a register transfer level (RTL) input file describing an integrated circuit design; parsing and translating the RTL input file into a plurality of Boolean logic equations; translating the plurality of Boolean logic equations into a plurality of logic primitives; placing the plurality of logic primitives into a floorplan of the integrated circuit design, wherein the placement of the plurality of logic primitives defines wire interconnects; and optimizing each of the plurality of Boolean logic equations in response to wire costs and wire timing delays.