The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Jul. 20, 2023
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Thaddeus Clay Mccracken, Mosier, OR (US);

Ankush Sood, Los Gatos, CA (US);

Yifeng Wang, Fremont, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/398 (2020.01); G06F 30/323 (2020.01); G06F 30/327 (2020.01); G06F 30/3323 (2020.01); G06F 30/337 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/33 (2020.01); G06F 30/323 (2020.01); G06F 30/327 (2020.01); G06F 30/3323 (2020.01); G06F 30/337 (2020.01);
Abstract

A method for incremental synthesis of a changed RTL design. A current RTL design and an implementation of a previous RTL design are processed to generate reuse information identifying one or more reusable design entities of the implementation of the previous register-transfer level design. An implementation of the current RTL design is generated by processing design entities of the current RTL design to generate synthesized logic corresponding to the design entities of the current RTL design, and combining the one or more reusable design entities with the synthesized logic based on the reuse information.


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