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For the Inventor, By the Inventor

Hillsboro, OR, United States of America

Amaresh Pangal

This inventor holds 8 USPTO granted patents. Top assignee: Intel Corporation. Active years: 2002-2008.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Amaresh Pangal. Retrieved from https://idiyas.com/inventor/amaresh-pangal

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 8

% Patents Active = 37.5

Average Co-Inventor Count = 2.2

ph-index = 5

Forward Citations = 76(Granted Patents)


Company Filing History:

goldMedal8 out of 56,290 
 
Intel Corporation
 patents

Years Active: 2002-2008

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8 patents (USPTO):Explore Patents
1. 7328361 - Digital bus synchronizer for generating read reset signal (2008-02-05),
2. 7222208 - Simultaneous bidirectional port with synchronization circuit to synchronize the port with another port (2007-05-22),
3. 7080111 - Floating point multiply accumulator (2006-07-18),
4. 6901526 - Digital bus synchronizer for generating read reset signal (2005-05-31),
5. 6889241 - Floating point adder (2005-05-03),
6. 6779013 - Floating point overflow and sign detection (2004-08-17),
7. 6448811 - Integrated circuit current reference (2002-09-10),
8. 6445170 - Current source with internal variable resistance and control loop for reduced process sensitivity (2002-09-03),

Title: Innovator Amaresh Pangal: Pioneering Digital Synchronization Technologies

Introduction

Amaresh Pangal is a notable inventor based in Hillsboro, Oregon. She has made significant contributions to the field of digital synchronization technologies, holding a total of 8 patents. Her work primarily focuses on enhancing communication systems through innovative designs and solutions.

Latest Patents

One of Amaresh Pangal's latest patents is a digital bus synchronizer for generating a read reset signal. This invention involves a digital bus that includes a transmitter unit, a receiver unit, and a transmission medium that connects the two. The receiver unit features a first-in-first-out (FIFO) unit and a synchronizer unit that processes information from the transmitter. The synchronizer generates a read reset signal that is precisely timed with respect to multiple write clock signals and a sample clock signal, ensuring minimal latency.

Another significant patent is for a simultaneous bidirectional port with a synchronization circuit. This invention allows for synchronization between two simultaneous data ports connected to the same bus. The synchronization circuit includes an output driver with imbalanced output impedance and a receiver that incorporates input hysteresis. This design ensures that both ports are properly initialized before communication begins, enhancing the reliability of data exchange.

Career Highlights

Amaresh Pangal is currently employed at Intel Corporation, where she continues to innovate and develop cutting-edge technologies. Her work at Intel has positioned her as a key player in the advancement of digital communication systems.

Collaborations

Throughout her career, Amaresh has collaborated with talented individuals such as Matthew B. Haycock and Dinesh Somasekhar. These collaborations have fostered a creative environment that has led to the development of groundbreaking technologies.

Conclusion

Amaresh Pangal's contributions to digital synchronization technologies exemplify her innovative spirit and dedication to advancing communication systems. Her patents reflect her expertise and commitment to enhancing the efficiency and reliability of digital communication.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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