The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2006
Filed:
Jun. 04, 2001
Amaresh Pangal, Hillsboro, OR (US);
Dinesh Somasekhar, Hillsboro, OR (US);
Shekhar Y. Borkar, Beaverton, OR (US);
Sriram R. Vangal, Hillsboro, OR (US);
Amaresh Pangal, Hillsboro, OR (US);
Dinesh Somasekhar, Hillsboro, OR (US);
Shekhar Y. Borkar, Beaverton, OR (US);
Sriram R. Vangal, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.