The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2005

Filed:

Jun. 04, 2001
Applicants:

Amaresh Pangal, Hillsboro, OR (US);

Dinesh Somasekhar, Hillsboro, OR (US);

Sriram R. Vangal, Hillsboro, OR (US);

Yatin V. Hoskote, Portland, OR (US);

Inventors:

Amaresh Pangal, Hillsboro, OR (US);

Dinesh Somasekhar, Hillsboro, OR (US);

Sriram R. Vangal, Hillsboro, OR (US);

Yatin V. Hoskote, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F007/50 ;
U.S. Cl.
CPC ...
Abstract

A floating point adder circuit includes an exponent path and a mantissa path. The exponent path includes a comparator to compare two three-bit exponents. The two exponents are each incremented, and a resultant exponent is chosen from one of the two original exponents or one of the incremented exponents. The mantissa path includes an adder to add mantissas, and an adder bypass path to select one of the mantissas in lieu of performing an addition. The mantissa path also includes constant shifters that conditionally shift the mantissas right by thirty-two bit positions.


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