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For the Inventor, By the Inventor

Yamato, Japan

Akashi Satoh

This inventor holds 15 USPTO granted patents. Top assignee: International Business Machines Corporation. Active years: 1995-2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Akashi Satoh. Retrieved from https://idiyas.com/inventor/akashi-satoh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 15

% Patents Active = 80.0

Average Co-Inventor Count = 2.2

ph-index = 9

Forward Citations = 251(Granted Patents)


Location History:

  • Kamifukuoka, JP (1996 - 1998)
  • Kanagawa-ken, JP (1999 - 2001)
  • Yamato, JP (1995 - 2012)

Company Filing History:

goldMedal15 out of 166,351 
 
International Business Machines Corporation
 patents

Years Active: 1995-2012

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15 patents (USPTO):Explore Patents
1. 8244790 - Multiplier and cipher circuit (2012-08-14),
2. 7460666 - Combinational circuit, encryption circuit, method for constructing the same and program (2008-12-02),
3. 7336887 - Content play back, information processing, and play back restriction (2008-02-26),
4. 6772942 - Arithmetic circuit to increase the speed of a modular multiplication for a public key system for encryption (2004-08-10),
5. 6735612 - Carry skip adder (2004-05-11),
6. 6317769 - Apparatus for calculating of Bc (mod n) with repeatedly shifting a holding value (2001-11-13),
7. 6199091 - Carry skip adder (2001-03-06),
8. 5928315 - Apparatus and method for calculating B.sup.c (mod n) (1999-07-27),
9. 5877714 - Search circuit for data compression (1999-03-02),
10. 5844910 - Flash-erase-type nonvolatile semiconductor storage device (1998-12-01),
11. 5787493 - Control method and apparatus for direct execution of a program on an (1998-07-28),
12. 5740097 - Content-addressable-memory control circuit (1998-04-14),
13. 5546402 - Flash-erase-type nonvolatile semiconductor storage device (1996-08-13),
14. 5509018 - Flash-erase-type nonvolatile semiconductor storage device (1996-04-16),
15. 5448733 - Data search and compression device and method for searching and (1995-09-05),

Title: Akashi Satoh: Innovator in Circuit Design

Introduction

Akashi Satoh is a prominent inventor based in Yamato, Japan, known for his significant contributions to the field of circuit design. With a total of 15 patents to his name, Satoh has made remarkable advancements in the areas of multipliers and encryption circuits.

Latest Patents

One of his latest patents is a multiplier circuit that incorporates a Wallace tree block and a carry propagation adder. This innovative design features a sum calculation block that adds partial products for each digit, along with a carry calculation block that processes carries obtained during the addition. In cases of multiplication over an extension field (finite field GF(2)), the result from the sum calculation block is outputted. The carry propagation adder then combines this result with the output from the carry calculation block. Additionally, Satoh has developed a combinational circuit and encryption circuit that includes an S-Box and a method for constructing an RO-BDD to define the configuration of the combinational circuit.

Career Highlights

Satoh is currently employed at International Business Machines Corporation (IBM), where he continues to innovate and push the boundaries of technology. His work has been instrumental in enhancing the efficiency and speed of circuit designs.

Collaborations

Throughout his career, Satoh has collaborated with notable colleagues, including Hideto Niijima and Yoshinao Kobayashi, contributing to various projects that have advanced the field of circuit design.

Conclusion

Akashi Satoh's contributions to circuit design and his innovative patents have established him as a key figure in the industry. His work continues to influence advancements in technology and circuit efficiency.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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