The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 1998
Filed:
Nov. 28, 1995
Akashi Satoh, Yamato, JP;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A timing control signal SR is made low to switch on a P-MOSFET and switch off an N-MOSFET, and with an N-MOSFET as a boundary, a voltage V.sub.MATCHI on the side of a NOT circuit of a match-line is pulled up to a power supply voltage V.sub.DD. During this, a comparison operation is done in a content addressable memory cell, and an N-MOSFET is switched on or off according to the result of comparison. Next, the control signal SR goes to a logic high level, so the P-MOSFET is switched off and the N-MOSFET is switched on. As a result, if the N-MOSFET is on, the voltages V.sub.MATCHI and V.sub.MATCH will be reduced to a ground level, but the through current is prevented because the P-MOSFET is off. If the N-MOSFET is off, the V.sub.MATCH will be pulled up to V.sub.DD -V.sub.tn (V.sub.tn is the threshold voltage of the N-MOSFET), the V.sub.MATCHI will be held to V.sub.DD by the NOT circuit and the P-MOSFET, and a signal representative of a result of comparison will be output from the NOT circuit. Also, by the interval of the N-MOSFET, the parasitic capacitance of the portion on the side of the content addressable memory cell of the match-line with the MOSFET as a boundary disappears from the portion on the side of the pull-up means from the portion on the side of the NOT circuit with the voltage drop element as a boundary, so the pull-up of the portion on the side of the NOT circuit with the MOSFET as a boundary becomes fast.