The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2004

Filed:

Oct. 30, 2000
Applicant:
Inventors:

Yoshinao Kobayashi, Hiratsuka, JP;

Akashi Satoh, Yamato, JP;

Seiji Munetoh, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/50 ;
U.S. Cl.
CPC ...
G06F 7/50 ;
Abstract

A carry skip adder has a plurality of ripple adders, in which at least one part of the plurality of ripple adders is divided into a plurality of groups, and a carry signal is transferred from one group to one upper group. In addition, a circuit for calculating C=C +F*C is included, in which the C denotes a carry signal from the one group to the one upper group, and the F denotes a signal indicating whether or not outputs of all adders in the one upper group are 1s, and the C denotes a carry signal associated with the most upper ripple adder in the one upper group. In a group including two or more ripple adders, a plurality of ripple adders in the group are organized into a plurality of sub-groups, and a carry signal is transferred from one sub-group to one upper sub-group, a circuit for calculating C =C +F *C is included, in which C denotes a carry signal from one sub-group to the one upper sub-group, and F denotes a signal indicating whether or not outputs of all adders in the one upper sub-group are 1s, and C denotes a carry signal associated with the most upper ripple adder in the one upper sub-group.


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