Search circuit for data compression

Abstract

To compress data at high speed, a search character is input to a write buffer 56 in sequence. Each of content addressable memory (CAM) cell rows compares the search character with character data stored therein and outputs the comparison result through a match line MATCH to a comparison result control circuit 60 every time. The comparison result is held in sequence to latches 82 and 84. When a signal ORFB input to a signal generation circuit 64 is low, the circuit 86 outputs the logical product between the output of the latch 82 and the output of the latch 88 of the preceding stage to a priority encoder 74 through a latch 88 and also to an OR circuit 90. When the signal ORFB is high, the circuit 86 outputs the logical product between the output of the latch 82 and the output of the latch 84 of the preceding stage to the priority encoder 74 through the latch 88 and also to the OR circuit 90. The encoder 74 outputs the logical sum of input signals as a match signal MSIG0 representative of the comparison result, and likewise an encoder 76 outputs the logical sum of input signals as a match signal MSIG. The signal output from the OR circuit 90 is input through a latch 92 and an OR circuit 94 to each signal generation circuit 80 as a signal ORFB. With this arrangement, the length of a path through which a signal passes in one cycle of a clock is reduced to half and therefore data compression can be performed at high speed.