Bengaluru, India

Adithya B S

This inventor holds 1 USPTO granted patent. Top assignee: Intel Corporation. Active years: 2022.


% Patents Active = 100.0

Average Co-Inventor Count = 10.0

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2022

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1 patent (USPTO):Explore Patents

Title: Adithya B S: Innovator in Integrated Circuit Technology

Introduction

Adithya B S is a prominent inventor based in Bengaluru, India. He has made significant contributions to the field of integrated circuits, particularly in the area of die-to-die interconnect technology. His innovative work has led to the development of a patent that enhances the testing capabilities of three-dimensional integrated circuits.

Latest Patents

Adithya holds a patent titled "Test architecture for die to die interconnect for three dimensional integrated circuits." This invention features a die-to-die repeater circuit that includes a transmit circuit coupled to a die-to-die interconnect. The transmit circuit incorporates at least one flip flop functioning as part of a linear feedback shift register (LFSR) to transmit values across the interconnect for design for test (DFT) purposes. Additionally, a receive circuit is included, which also features at least one flip flop functioning as part of a multiple input shift register (MISR). This innovative architecture is crucial for ensuring the proper operation of die-to-die interconnects.

Career Highlights

Adithya is currently employed at Intel Corporation, where he continues to push the boundaries of technology in integrated circuits. His work at Intel has allowed him to collaborate with some of the brightest minds in the industry, contributing to advancements in semiconductor technology.

Collaborations

Some of Adithya's notable coworkers include Wei Ming Lim and Amit D Sanghani. Their collaborative efforts have further enhanced the innovative environment at Intel Corporation.

Conclusion

Adithya B S is a key figure in the realm of integrated circuit technology, with a focus on improving testing methodologies for advanced semiconductor designs. His contributions are paving the way for future innovations in the field.

Profile summary based on public USPTO records.
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