Intel Corporation

Adithya B S

Amit D Sanghani

Sreejit Chakravarty

Fei Su

Anubhav Sinha

Rakesh Reddy Kandula

Puneet Gupta

Terrence Huat Hin Tan

Wei Ming Lim

Sudheer V Badana

A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).

Test architecture for die to die interconnect for three dimensional integrated circuits

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Bengaluru, India

Adithya B S