The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2022

Filed:

Sep. 27, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sreejit Chakravarty, San Jose, CA (US);

Fei Su, Folsom, CA (US);

Puneet Gupta, San Jose, CA (US);

Wei Ming Lim, Bayan Lepas, MY;

Terrence Huat Hin Tan, Georgetown, MY;

Amit Sanghani, San Jose, CA (US);

Anubhav Sinha, Hyderabad, IN;

Sudheer V Badana, Srikakulam, IN;

Rakesh Kandula, Bengaluru, IN;

Adithya B. S., Bengaluru, IN;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/12 (2006.01); G11C 29/48 (2006.01); H01L 23/538 (2006.01); H03K 17/56 (2006.01); H03K 17/00 (2006.01); G11C 29/50 (2006.01); G11C 29/02 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G11C 29/1201 (2013.01); G11C 29/025 (2013.01); G11C 29/48 (2013.01); G11C 29/50 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H03K 17/002 (2013.01); H03K 17/56 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 25/0657 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01);
Abstract

A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).


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