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For the Inventor, By the Inventor

Wappingers Falls, NY, United States of America

Adil Bhanji

USPTO Granted Patents = 10 

Average Co-Inventor Count = 5.1

ph-index = 3

Forward Citations = 32(Granted Patents)


Company Filing History:

goldMedal10 out of 164,108 
 
International Business Machines Corporation
 patents

Years Active: 2010-2021

where 'Filed Patents' based on already Granted Patents

10 patents (USPTO):
1. 10970455 - Apportionment aware hierarchical timing optimization (2021-04-06),
2. 10831954 - Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs (2020-11-10),
3. 10318683 - Clock domain-independent abstracts (2019-06-11),
4. 10169503 - Callback based constraint processing for clock domain independence (2019-01-01),
5. 9977850 - Callback based constraint processing for clock domain independence (2018-05-22),
6. 9607124 - Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints (2017-03-28),
7. 8185371 - Modeling full and half cycle clock variability (2012-05-22),
8. 8122404 - Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits (2012-02-21),
9. 8103997 - Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits (2012-01-24),
10. 7788617 - Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis (2010-08-31),

Title: The Innovative Contributions of Adil Bhanji

Introduction

Adil Bhanji is a prominent inventor based in Wappingers Falls, NY (US). He has made significant contributions to the field of VLSI design, holding a total of 10 patents. His work focuses on optimizing electronic design automation, which is crucial for the advancement of integrated circuit technology.

Latest Patents

Among his latest patents is the "Apportionment Aware Hierarchical Timing Optimization." This invention involves methods and apparatus for creating an improved VLSI design. In this process, in-context timing analysis of a nominal VLSI design is performed, and apportionment adjustments are determined for sub-blocks of the design. The derived slack adjustments are applied to simulate a post-optimization version of the sub-block, ultimately leading to an improved VLSI design.

Another notable patent is the "Technology Lookup Table-Based Default Assertion Generation and Consumption for Timing Closure of VLSI Designs." This innovation enhances the efficiency of electronic design automation by utilizing a data structure that characterizes a hierarchical integrated circuit design. The process involves obtaining wire specifications for ports in sub-blocks and consulting technology-specific lookup tables to optimize the design.

Career Highlights

Adil Bhanji is currently employed at International Business Machines Corporation (IBM), where he continues to push the boundaries of VLSI design. His expertise in timing optimization and electronic design automation has made him a valuable asset to the company.

Collaborations

Throughout his career, Adil has collaborated with notable coworkers such as Debjit Sinha and Kerim Kalafala. These collaborations have further enriched his work and contributed to the success of various projects.

Conclusion

Adil Bhanji's innovative contributions to VLSI design and electronic design automation have established him as a leading inventor in his field. His patents reflect a commitment to improving technology and enhancing the efficiency of integrated circuit designs.

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