The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2012
Filed:
Apr. 20, 2009
Debjit Sinha, Wappingers Falls, NY (US);
Soroush Abbaspour, Ossining, NY (US);
Adil Bhanji, Wappingers Falls, NY (US);
Jeffrey M. Ritzinger, Chippewa Falls, WI (US);
Debjit Sinha, Wappingers Falls, NY (US);
Soroush Abbaspour, Ossining, NY (US);
Adil Bhanji, Wappingers Falls, NY (US);
Jeffrey M. Ritzinger, Chippewa Falls, WI (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.