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Hauppauge, NY, United States of America

Vishay General Semiconductor, Inc.

Calculating rank

USPTO Granted Patents = 56

% Expired Patents = 28.6

EPO Patents = 22

Trademarks = 4

Forward Citations = 112

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58 inventors (with patents filed for the assignee):

Chih-Ping Peng (10 out of 10 patents)

Yih-Yin Lin (10 out of 11 patents)

Wan-Lan Chiang (9 out of 9 patents)

4. Ta-Te Chou (9 out of 9 patents)

5. Lung-Ching Kao (8 out of 8 patents)

6. Xian Li (8 out of 8 patents)

7. Yong-Qi Tian (8 out of 8 patents)

8. Shih-Kuan Chen (6 out of 7 patents)

9. Xiong-Jie Zhang (6 out of 6 patents)

10. Hai Fu (6 out of 6 patents)

11. Max Sk Chen (5 out of 10 patents)

12. Kuang Hann Lin (5 out of 7 patents)

13. Huiying Ding (4 out of 4 patents)

14. Junfeng Liu (4 out of 4 patents)

15. Longnan Jin (4 out of 4 patents)

Core Competencies:

Semiconductor Package

Side-Wall Plating

GaN-Based Schottky Diode

Trench MOS Device

Voltage Sustaining Layer

Zener Diode

Transient Voltage Suppressor

Power Semiconductor Device

Planar Diode

Heat Dissipation

Conductive Film

Lead Frame

56 patents: Sort by Forward Citations

1. 11876003 - Semiconductor package and packaging process for side-wall plating with a conductive film (2024-01-16),

2. 11764075 - Package assembly for plating with selective molding (2023-09-19),

3. 11450534 - Packaging process for side-wall plating with a conductive film (2022-09-20),

4. 11393699 - Packaging process for plating with selective molding (2022-07-19),

5. 10163762 - Lead frame with conductive clip for mounting a semiconductor die with reduced clip shifting (2018-12-25),

6. 10043676 - Local semiconductor wafer thinning (2018-08-07),

7. 9966429 - Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current (2018-05-08),

8. 9537017 - Process for forming a planar diode using one mask (2017-01-03),

9. 9368584 - Gallium nitride power semiconductor device having a vertical structure (2016-06-14),

10. 9331142 - Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current (2016-05-03),

11. 9281417 - GaN-based schottky diode having large bond pads and reduced contact resistance (2016-03-08),

12. 9263820 - Electrical press-fit pin for a semiconductor module (2016-02-16),

13. 9202935 - Zener diode haviing a polysilicon layer for improved reverse surge capability and decreased leakage current (2015-12-01),

14. 9178015 - Trench MOS device having a termination structure with multiple field-relaxation trenches for high voltage applications (2015-11-03),

15. 9041188 - Axial semiconductor package (2015-05-26),

Company Overview

Vishay General Semiconductor, Inc., based in Hauppauge, NY, specializes in the development and manufacturing of advanced semiconductor packaging solutions. The company focuses on core technologies such as semiconductor packages, side-wall plating, and various power semiconductor devices, including GaN-based Schottky diodes and trench MOS devices. Vishay's innovations also encompass voltage sustaining layers, Zener diodes, and transient voltage suppressors, catering to a diverse range of applications across multiple industries.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

56 Patents

#8 in Hauppauge, NY

#388 in New York

#6,362 in US

#12,761 in the World

Hauppauge, NY, United States of America

Vishay General Semiconductor, Inc.

Forward Citations = 112

58 inventors:

Chih-Ping Peng (10 out of 10 patents)

Yih-Yin Lin (10 out of 11 patents)

Wan-Lan Chiang (9 out of 9 patents)

4. Ta-Te Chou (9 out of 9 patents)

5. Lung-Ching Kao (8 out of 8 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Vishay General Semiconductor, Inc.. Retrieved from https://idiyas.com/company/vishay-general-semiconductor

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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