The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Jun. 16, 2022
Applicant:

Vishay General Semiconductor, Llc, Malvern, PA (US);

Inventors:

Huiying Ding, Tianjin, CN;

Junfeng Liu, Tianjin, CN;

Longnan Jin, Tianjin, CN;

Heinrich Karrer, Regau, AT;

Thomas Schmidt, Leonding, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4839 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/3121 (2013.01); H01L 23/49534 (2013.01); H01L 24/48 (2013.01); H01L 2224/48245 (2013.01); H01L 2924/173 (2013.01);
Abstract

Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame may include a plurality of lead sets, each lead set including leads having a die surface and a plating surface, vias between adjacent lead sets in a first direction, and an integrated circuit die arranged on the die surface of each die lead. A mold chase may be applied to the plating surfaces, the mold chase including mold chase extensions extending into the vias between each adjacent lead set in the first direction, each mold chase extension having a peak surface. The lead frame assembly may be partially embedded in a mold encapsulation such that portions of the mold encapsulation contact the peak surfaces. The mold chase may be removed to expose the vias containing sidewalls and the plating surfaces and the sidewalls may be plated with an electrical plating.


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