The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Jan. 10, 2014
Applicant:

Vishay General Semiconductor Llc, Hauppauge, NY (US);

Inventors:

Yi-Yu Lin, New Taipei, TW;

Chun-Chueh Chang, Yilan County, TW;

Pu Ju Kung, New Taipei, TW;

Assignee:

Vishay General Semiconductor LLC, Hauppauge, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/872 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 29/0661 (2013.01); H01L 29/407 (2013.01); H01L 29/66143 (2013.01); H01L 29/8725 (2013.01);
Abstract

A termination structure for a semiconductor device includes a semiconductor substrate having an active region and a termination region. Two or more trench cells are located in the termination region and extend from a boundary of the active region toward an edge of the semiconductor substrate. A termination trench is formed in the termination region on a side of the trench cells remote from the active region. A conductive spacer is located adjacent to a sidewall of the termination trench nearest the trench cells. A first oxide layer is formed in the termination trench and contacts a sidewall of the conductive spacer. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region and the termination region.


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