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Forward Citations = 984

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11 inventors (with patents filed for the assignee):

John Gregory Favor (6 out of 117 patents)

David R Stiles (6 out of 39 patents)

Korbin S Van Dyke (6 out of 76 patents)

4. Harold L McFarland (4 out of 14 patents)

5. William A Stutz (1 out of 18 patents)

6. Shrenik M Mehta (1 out of 9 patents)

7. Dale Robert Greenley (1 out of 18 patents)

8. Walstein Bennett Smith, Iii (1 out of 7 patents)

9. Robert Alan Cargnoni (1 out of 50 patents)

10. Allen P Ho (1 out of 3 patents)

11. Philip Y Pun (1 out of 2 patents)

10 patents: Sort by Forward Citations

1. 5479124 - Slew rate controller for high speed bus (1995-12-26),

2. 5388227 - Transparent data bus sizing (1995-02-07),

3. 5369748 - Bus arbitration in a dual-bus architecture where one bus has relatively (1994-11-29),

4. 5327547 - Two-level branch prediction cache (1994-07-05),

5. 5230068 - Cache memory system for dynamically altering single cache memory line as (1993-07-20),

6. 5226130 - Method and apparatus for store-into-instruction-stream detection and (1993-07-06),

7. 5226126 - Processor having plurality of functional units for orderly retiring (1993-07-06),

8. 5163140 - Two-level branch prediction cache (1992-11-10),

9. 5125093 - Interrupt control for multiprocessor computer system (1992-06-23),

10. 5093778 - Integrated single structure branch prediction cache (1992-03-03),

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Profile summary based on public USPTO records.

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USPTO Data Jan 1 1976 - Oct 6 2026

10 Patents

#532 in San Jose, CA

#7,108 in California

#29,839 in US

#55,986 in the World

San Jose, CA, United States of America

Nexgen Microsystems