The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 1992
Filed:
Aug. 14, 1990
Harold L McFarland, San Jose, CA (US);
Nexgen Microsystems, San Jose, CA (US);
Abstract
A technique that efficiently allocates the servicing of interrupts among a plurality of CPUs in a multiprocessor computer system requires no change in software that was written for a system with one CPU and one PIC. Symmetric and asymmetric configurations contemplate a primary CPU (15a) and one or more secondary CPU's (15b-d) responding to and servicing multiple sets of interrupts. Both configurations include interrupt supervisory logic to support such operation. The symmetric configuration provides a PIC (20a-d) for each CPU in the system. All the PICs are located at the same I/O address, and separate provision is made to specify which PIC is to respond to an interrupt acknowledge cycle initiated by a particular CPU. The asymmetric configuration of the present invention provides PIC (20a) for the primary CPU (15a) only. That PIC's interrupt line is communicated only to the primary CPU. Another mechanism, such as an ATTN facility (95), is provided to drive the secondary CPU's interrupt inputs. Since the secondary CPUs lack PICs there is provided logic (48) that responds to an interrupt acknowledge operation from any of the secondary CPUs by driving a fixed, interrupt vector onto the data bus.