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Forward Citations = 209

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9 inventors (with patents filed for the assignee):

Tushar R Gheewala (9 out of 23 patents)

Robert J Lipp (4 out of 22 patents)

Susheel J Chandra (2 out of 2 patents)

4. Rustam J Mehta (2 out of 7 patents)

5. Timothy Saxe (1 out of 5 patents)

6. Thomas V Ferry (1 out of 6 patents)

7. Kerry M Pierce (1 out of 15 patents)

8. Hector R Sucar (1 out of 1 patent)

9. Prab Varma (1 out of 1 patent)

13 patents: Sort by Forward Citations

1. 5495486 - Method and apparatus for testing integrated circuits (1996-02-27),

2. 5471152 - Storage element for delay testing (1995-11-28),

3. 5436801 - Method and structure for routing power for optimum cell utilization with (1995-07-25),

4. 5230001 - Method for testing a sequential circuit by splicing test vectors into (1993-07-20),

5. 5206862 - Method and apparatus for locally deriving test signals from previous (1993-04-27),

6. 5202624 - Interface between IC operational circuitry for coupling test signal from (1993-04-13),

7. 5179534 - Method and apparatus for setting desired logic state at internal point (1993-01-12),

8. 5157627 - Method and apparatus for setting desired signal level on storage element (1992-10-20),

9. 5065090 - Method for testing integrated circuits having a grid-based, 'cross-check' t (1991-11-12),

10. 5038349 - Method for reducing masking of errors when using a grid-based, (1991-08-06),

11. 5037771 - Method for implementing grid-based crosscheck test structures and the (1991-08-06),

12. 4975640 - Method for operating a linear feedback shift register as a serial shift (1990-12-04),

13. 4937826 - Method and apparatus for sensing defects in integrated circuit elements (1990-06-26),

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USPTO Data Jan 1 1976 - Dec 2 2025

13 Patents

#423 in San Jose, CA

#5,470 in California

#23,090 in US

#43,583 in the World

San Jose, CA, United States of America

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