The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 1990

Filed:

Sep. 09, 1988
Applicant:
Inventors:

Tushar R Gheewala, Cupertino, CA (US);

Robert J Lipp, Los Gatos, CA (US);

Assignee:

CrossCheck Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 221 ; 371 214 ; 371 151 ;
Abstract

An apparatus for testing for faults in an integrated circuit is attached to sense lines which are coupled to output nodes of logic gates of a test structure within an integrated circuit, such as a 'Cross-Check' test structure built into an integrate circuit apparatus. A related method provide precharging of the sense lines to a known signal level prior to using the sense lines to sense the signal level at a test point. The apparatus combined with sense amplifiers or comparators attached to the sense lines may adjust detection levels of the comparators synchronously to test for either an output 'one' minimum level (VOH) or output 'zero' maximum level (VOL) to test for other classes of faults. The apparatus attached to the sense lines may inject charge into an output node of a logic gate at preselected times in a test sequence to modify the signal level at that output node to test for faults. A method according to the invention includes path sensitization whereby test patterns can be reduced to Boolean expressions.


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