The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Aug. 29, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yung-Hsu Wu, Taipei, TW;

Cheng-Hsiung Tsai, Zhunan Township, TW;

Yu-Sheng Chang, Taipei, TW;

Chia-Tien Wu, Taichung, TW;

Chung-Ju Lee, Hsinchu, TW;

Yung-Sung Yen, New Taipei, TW;

Chun-Kuang Chen, Guanxi Township, TW;

Tien-I Bao, Dayuan Township, TW;

Ru-Gun Liu, Zhubei, TW;

Shau-Lin Shue, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76877 (2013.01); H01L 21/0228 (2013.01); H01L 21/02115 (2013.01); H01L 21/02186 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76808 (2013.01); H01L 21/76811 (2013.01); H01L 23/5283 (2013.01); H01L 21/76816 (2013.01); H01L 2221/1063 (2013.01);
Abstract

Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A spacer material layer is formed over the plurality of trenches. A via pattern including a plurality of openings is formed over the spacer material layer and plurality of trenches. Via holes can be etched in the dielectric layer using the via pattern and spacer material layer as a masking element.


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