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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9972554 B1

PDFFull Text
Date of Patent:
May. 15, 2018

Filed:

Feb. 15, 2017

Wafer level chip scale package having continuous through hole via configuration and fabrication method thereof

Applicant:

Powertech Technology Inc., Hsinchu County, TW;

Inventors:

Li-Chih Fang, Hsinchu County, TW;

Chia-Chang Chang, Hsinchu County, TW;

Hung-Hsin Hsu, Hsinchu County, TW;

Wen-Hsiung Chang, Hsinchu County, TW;

Kee-Wei Chung, Hsinchu County, TW;

Chia-Wen Lien, Hsinchu County, TW;

Assignee:

POWERTECH TECHNOLOGY INC., Hsinchu County, TW;

Attorney:

Winston Hsu

Primary Examiner:

Ismail Muse

Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 23/52 (2006.01); H01L 23/48 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3114 (2013.01); H01L 21/56 (2013.01); H01L 21/76898 (2013.01); H01L 23/3121 (2013.01); H01L 23/481 (2013.01); H01L 23/49827 (2013.01); H01L 23/562 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 27/14618 (2013.01); H01L 27/14627 (2013.01); H01L 27/14632 (2013.01); H01L 27/14636 (2013.01); H01L 2224/0237 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/1134 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/13016 (2013.01); H01L 2224/13027 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/0132 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.

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