Kee-Wei Chung

Title: Kee-Wei Chung: Innovator in Wafer Level Chip Scale Packaging

Introduction

Kee-Wei Chung is a notable inventor based in Hsinchu County, Taiwan. He has made significant contributions to the field of semiconductor packaging, particularly through his innovative designs and methods. His work has led to advancements in the efficiency and functionality of electronic devices.

Latest Patents

Kee-Wei Chung holds a patent for a "Wafer level chip scale package having continuous through hole via configuration and fabrication method thereof." This invention involves a wafer level chip scale package (WLCSP) that includes a device chip, a carrier chip, an offset pad, a conductive spacing bump, and a through hole via (THV). The device chip is attached to the carrier chip, with the offset pad located on the first surface of the device chip. The conductive spacing bump is formed on the offset pad, while the through hole via features a through hole and a hole metal layer. This configuration allows the through hole to penetrate both the carrier chip and the device chip, with the hole metal layer in contact with the offset pad.

Career Highlights

Kee-Wei Chung is currently employed at Powertech Technology Inc., a leading company in the semiconductor packaging industry. His work at Powertech has allowed him to focus on innovative solutions that enhance the performance of electronic components. His patent reflects his commitment to advancing technology in this field.

Collaborations

Kee-Wei Chung has collaborated with talented coworkers, including Li-Chih Fang and Chia-Chang Chang. These collaborations have fostered a creative environment that encourages innovation and the development of cutting-edge technologies.

Conclusion

Kee-Wei Chung's contributions to wafer level chip scale packaging demonstrate his expertise and dedication to innovation in the semiconductor industry. His patent showcases a significant advancement that can impact the future of electronic device manufacturing.