The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Oct. 26, 2016
Applicant:

Siliconware Precision Industries Co., Ltd., Taichung, TW;

Inventors:

Yu-Cheng Pai, Taichung, TW;

Chun-Hsien Lin, Taichung, TW;

Shih-Chao Chiu, Taichung, TW;

Wei-Chung Hsiao, Taichung, TW;

Ming-Chen Sun, Taichung, TW;

Tzu-Chieh Shen, Taichung, TW;

Chia-Cheng Chen, Taichung, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/683 (2006.01); H05K 3/40 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H05K 3/46 (2006.01); H05K 3/20 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6835 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 23/498 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H05K 3/4007 (2013.01); H01L 24/17 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H05K 3/20 (2013.01); H05K 3/4682 (2013.01); H05K 2201/0367 (2013.01); H05K 2201/09563 (2013.01); H05K 2201/10674 (2013.01);
Abstract

A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.


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