The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Aug. 19, 2014
Applicants:

Pil-kyu Kang, Anyang-si, KR;

Byung Lyul Park, Seoul, KR;

Sunghee Kang, Seongnam-si, KR;

Taeseong Kim, Suwon-si, KR;

Taeyeong Kim, Suwon-si, KR;

Kwangjin Moon, Hwaseong-si, KR;

Jae-hwa Park, Yongin-si, KR;

Sukchul Bang, Yongin-si, KR;

Seongmin Son, Hwaseong-si, KR;

Jin Ho an, Seoul, KR;

Ho-jin Lee, Seoul, KR;

Jeonggi Jin, Seoul, KR;

Inventors:

Pil-Kyu Kang, Anyang-si, KR;

Byung Lyul Park, Seoul, KR;

SungHee Kang, Seongnam-si, KR;

Taeseong Kim, Suwon-si, KR;

Taeyeong Kim, Suwon-si, KR;

Kwangjin Moon, Hwaseong-si, KR;

Jae-Hwa Park, Yongin-si, KR;

Sukchul Bang, Yongin-si, KR;

Seongmin Son, Hwaseong-si, KR;

Jin Ho An, Seoul, KR;

Ho-Jin Lee, Seoul, KR;

Jeonggi Jin, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 23/48 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/7682 (2013.01); H01L 21/76898 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.


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