The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

Jul. 13, 2016
Applicant:

Invensas Corporation, San Jose, CA (US);

Inventors:

Rajesh Katkar, San Jose, CA (US);

Reynaldo Co, Santa Cruz, CA (US);

Scott McGrath, Scotts Valley, CA (US);

Ashok S. Prabhu, San Jose, CA (US);

Sangil Lee, Santa Clara, CA (US);

Liang Wang, Milpitas, CA (US);

Hong Shen, Palo Alto, CA (US);

Assignee:

Invensas Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 25/50 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/83005 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06582 (2013.01); H01L 2225/06589 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/1032 (2013.01); H01L 2924/1037 (2013.01); H01L 2924/10252 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1438 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/19107 (2013.01);
Abstract

A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip. The chip stack is mounted to substrate at an angle such that edge surfaces of the chips face a major surface of the substrate that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. An electrically conductive material electrically connects the chip terminals with corresponding substrate contacts.


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