The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

Oct. 06, 2016
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

James S. Sims, Tigard, OR (US);

Jon Henri, West Linn, OR (US);

Ramesh Chandrasekharan, Portland, OR (US);

Andrew John McKerrow, Lake Oswego, OR (US);

Seshasayee Varadarajan, Lake Oswego, OR (US);

Kathryn Merced Kelchner, Portland, OR (US);

Assignee:

LAM RESEARCH CORPORATION, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); C23C 16/02 (2006.01); C23C 16/34 (2006.01); C23C 16/50 (2006.01); C23C 16/455 (2006.01); H01J 37/32 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0228 (2013.01); C23C 16/0227 (2013.01); C23C 16/0272 (2013.01); C23C 16/345 (2013.01); C23C 16/45525 (2013.01); C23C 16/50 (2013.01); H01J 37/32082 (2013.01); H01J 37/32532 (2013.01); H01L 21/0217 (2013.01); H01L 21/02211 (2013.01); H01L 21/02274 (2013.01); H01J 2237/335 (2013.01); H01J 2237/3321 (2013.01);
Abstract

A method of depositing silicon nitride films on semiconductor substrates processed in a micro-volume of a plasma enhanced atomic layer deposition (PEALD) reaction chamber wherein a single semiconductor substrate is supported on a ceramic surface of a pedestal and process gas is introduced through gas outlets in a ceramic surface of a showerhead into a reaction zone above the semiconductor substrate, includes (a) cleaning the ceramic surfaces of the pedestal and showerhead with a fluorine plasma, (b) depositing a halide-free atomic layer deposition (ALD) oxide undercoating on the ceramic surfaces, (c) depositing a precoating of ALD silicon nitride on the halide-free ALD oxide undercoating, and (d) processing a batch of semiconductor substrates by transferring each semiconductor substrate into the reaction chamber and depositing a film of ALD silicon nitride on the semiconductor substrate supported on the ceramic surface of the pedestal.

Published as:
US9824884B1; US2018102245A1; WO2018067299A1; US10020188B2; TW201827637A; KR20190052154A; CN109891550A; KR102470170B1; KR20220159488A; CN117210798A; KR20240135683A; KR102857895B1; KR20250137197A;

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