The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2017
Filed:
Feb. 24, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Robert S. Chau, Beaverton, OR (US);
Suman Datta, Beaverton, OR (US);
Jack Kavalieros, Portland, OR (US);
Justin K. Brask, Portland, OR (US);
Mark L. Doczy, Portland, OR (US);
Matthew Metz, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/267 (2006.01); H01L 29/45 (2006.01); H01L 29/207 (2006.01); H01L 29/51 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 29/0847 (2013.01); H01L 29/207 (2013.01); H01L 29/267 (2013.01); H01L 29/452 (2013.01); H01L 29/517 (2013.01); H01L 29/66522 (2013.01); H01L 29/66636 (2013.01); H01L 29/7836 (2013.01); H01L 29/16 (2013.01);
Abstract
A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.