The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2017
Filed:
Apr. 30, 2015
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Shih-Wei Liang, Dajia Township, TW;
Bor-Rung Su, New Taipei, TW;
Chang-Pin Huang, Yangmei Township, TW;
Chien-Chia Chiu, Zhongli, TW;
Hsien-Ming Tu, Zhubei, TW;
Chun-Hung Lin, Taipei, TW;
Yu-Chia Lai, Zhunan Township, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes a first post-passivation interconnect (PPI) layer. The first PPI layer includes a landing pad and a shadow pad material proximate the landing pad. A polymer layer is over the first PPI layer, and a second PPI layer is over the polymer layer. The second PPI layer includes a PPI pad. The PPI pad is coupled to the landing pad by a via in the polymer layer. The shadow pad material is proximate the PPI pad and comprises a greater dimension than a dimension of the PPI pad. The shadow pad material is disposed laterally around the PPI pad.