The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Sep. 11, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Hongning Yang, Chandler, AZ (US);

Daniel J. Blomberg, Chandler, AZ (US);

Xu Cheng, Chandler, AZ (US);

Xin Lin, Phoenix, AZ (US);

Zhihong Zhang, Chandler, AZ (US);

Jiang-Kai Zuo, Chandler, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 21/22 (2006.01); H01L 21/768 (2006.01); H01L 29/36 (2006.01); H01L 27/02 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 21/22 (2013.01); H01L 21/76897 (2013.01); H01L 23/528 (2013.01); H01L 27/0251 (2013.01); H01L 29/1095 (2013.01); H01L 29/365 (2013.01); H01L 29/66689 (2013.01); H01L 29/7823 (2013.01);
Abstract

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area, and a body region disposed in the semiconductor substrate within the core device area, and in which a channel is formed during operation. The body region is electrically tied to the isolation contact region. The body region and the doped isolation barrier have a common conductivity type. The body region is electrically isolated from the doped isolation barrier within the core device area. The doped isolation barrier and the isolation contact region are not electrically tied to one another such that the doped isolation barrier is biased at a different voltage level than the isolation contact region.


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