The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Dec. 23, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Han Wui Then, Portland, OR (US);

Robert S. Chau, Beaverton, OR (US);

Sansaptak Dasgupta, Hillsboro, OR (US);

Marko Radosavljevic, Beaverton, OR (US);

Benjamin Chu-Kung, Portland, OR (US);

Seung Hoon Hoon Sung, Portland, OR (US);

Sanaz K. Gardner, Portland, OR (US);

Ravi Pillarisetty, Portland, OR (US);

Assignee:

Intel Coporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/20 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/8252 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/205 (2006.01); H01L 29/32 (2006.01); H01L 29/34 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 21/8252 (2013.01); H01L 21/84 (2013.01); H01L 27/0605 (2013.01); H01L 27/1211 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/32 (2013.01); H01L 29/34 (2013.01); H01L 29/66462 (2013.01); H01L 29/66522 (2013.01); H01L 29/66795 (2013.01);
Abstract

Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.


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