The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2017
Filed:
Mar. 05, 2014
Thomas J. DE Bonis, Tempe, AZ (US);
Lilia May, Chandler, AZ (US);
Rajen S. Sidhu, Chandler, AZ (US);
Mukul P. Renavikar, Chandler, AZ (US);
Ashay A. Dani, Chandler, AZ (US);
Edward R. Prack, Phoenix, AZ (US);
Carl L. Deppisch, Chandler, AZ (US);
Anna M. Prakash, Chandler, AZ (US);
James C. Matayabas, Jr., Gilber, AZ (US);
Jason Jieping Zhang, Chandler, AZ (US);
Srinivasa R. Aravamudhan, Beaverton, OR (US);
Chang Lin, Portland, OR (US);
Thomas J. De Bonis, Tempe, AZ (US);
Lilia May, Chandler, AZ (US);
Rajen S. Sidhu, Chandler, AZ (US);
Mukul P. Renavikar, Chandler, AZ (US);
Ashay A. Dani, Chandler, AZ (US);
Edward R. Prack, Phoenix, AZ (US);
Carl L. Deppisch, Chandler, AZ (US);
Anna M. Prakash, Chandler, AZ (US);
James C. Matayabas, Jr., Gilber, AZ (US);
Jason Jieping Zhang, Chandler, AZ (US);
Srinivasa R. Aravamudhan, Beaverton, OR (US);
Chang Lin, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.