The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

May. 15, 2013
Applicant:

Xintec Inc., Jhongli, Taoyuan County, TW;

Inventors:

Shu-Ming Chang, New Taipei, TW;

Yu-Ting Huang, Tainan, TW;

Tsang-Yu Liu, Zhubei, TW;

Yen-Shih Ho, Kaohsiung, TW;

Assignee:

XINTEC INC., Taoyuan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/78 (2006.01); H01L 23/48 (2006.01); B81B 7/00 (2006.01); H01L 23/00 (2006.01); H01L 21/683 (2006.01); H01L 23/60 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); B81B 7/007 (2013.01); H01L 21/78 (2013.01); H01L 23/481 (2013.01); H01L 24/92 (2013.01); B81B 2207/095 (2013.01); B81B 2207/096 (2013.01); H01L 21/6835 (2013.01); H01L 23/60 (2013.01); H01L 24/02 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/80 (2013.01); H01L 24/83 (2013.01); H01L 24/94 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/03002 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05617 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/08148 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13021 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/8385 (2013.01); H01L 2224/92 (2013.01); H01L 2224/94 (2013.01); H01L 2924/10155 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1461 (2013.01);
Abstract

An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed thereon, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.


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