The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2016
Filed:
Oct. 28, 2011
Kevin J. Lee, Beaverton, OR (US);
Mark T. Bohr, Aloha, OR (US);
Andrew W. Yeoh, Portland, OR (US);
Christopher M. Pelto, Beaverton, OR (US);
Hiten Kothari, Beaverton, OR (US);
Seshu V. Sattiraju, Portland, OR (US);
Hang-shing MA, Portland, OR (US);
Kevin J. Lee, Beaverton, OR (US);
Mark T. Bohr, Aloha, OR (US);
Andrew W. Yeoh, Portland, OR (US);
Christopher M. Pelto, Beaverton, OR (US);
Hiten Kothari, Beaverton, OR (US);
Seshu V. Sattiraju, Portland, OR (US);
Hang-Shing Ma, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.