The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2016

Filed:

Nov. 04, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Jianwei Peng, Albany, NY (US);

Hong Yu, Rexford, NY (US);

Zhao Lun, Ballston Lake, NY (US);

Tao Han, Clifton Park, NY (US);

Hsien-Ching Lo, Clifton Park, NY (US);

Basab Banerjee, Ballston Lake, NY (US);

Wen Zhi Gao, Rexford, NY (US);

Byoung-Gi Min, Cohoes, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8232 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/108 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 27/10879 (2013.01);
Abstract

A method of forming spacers and the resulting fin-shaped field effect transistors are provided. Embodiments include forming a silicon (Si) fin over a substrate; forming a polysilicon gate over the Si fin; and forming a spacer on top and side surfaces of the polysilicon gate, and on exposed upper and side surfaces of the Si fin, the spacer including: a first layer and second layer having a first dielectric constant, and a third layer formed between the first and second layers and having a second dielectric constant, wherein the second dielectric constant is lower than the first dielectric constant.


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