The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2016
Filed:
Oct. 11, 2013
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Hung-Chun Wang, Taichung, TW;
Ming-Hui Chih, Luzhou, TW;
Ping-Chieh Wu, New Taipei, TW;
Chun-Hung Wu, Hsinchu, TW;
Wen-Hao Liu, Zhubei, TW;
Cheng-Hsuan Huang, New Taipei, TW;
Cheng-Kun Tsai, Hsinchu, TW;
Wen-Chun Huang, Tainan, TW;
Ru-Gun Liu, Zhubei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.