The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2016
Filed:
Jan. 13, 2011
Jeffrey P. Bonn, Essex Junction, VT (US);
Brent A. Goplen, Underhill, VT (US);
Brian L. Kinsman, Essex Junction, VT (US);
Robert M. Rassel, Colchester, VT (US);
Edmund J. Sprogis, Williston, VT (US);
Daniel S. Vanslette, Fairfax, VT (US);
Jeffrey P. Bonn, Essex Junction, VT (US);
Brent A. Goplen, Underhill, VT (US);
Brian L. Kinsman, Essex Junction, VT (US);
Robert M. Rassel, Colchester, VT (US);
Edmund J. Sprogis, Williston, VT (US);
Daniel S. Vanslette, Fairfax, VT (US);
GlobalFoundries, Inc., Grand Cayman, KY;
Abstract
Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.