The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2016
Filed:
Apr. 07, 2011
Guang-yaw Hwang, Tainan, TW;
Chun-hsien Lin, Tainan, TW;
Hung-ling Shih, Chiayi County, TW;
Jiunn-hsiung Liao, Tainan, TW;
Zhi-cheng Lee, Tainan, TW;
Shao-hua Hsu, Taoyuan County, TW;
Yi-wen Chen, Tainan, TW;
Cheng-guo Chen, Changhua County, TW;
Jung-tsung Tseng, Tainan, TW;
Chien-ting Lin, Hsinchu, TW;
Tong-jyun Huang, Tainan, TW;
Jie-ning Yang, Ping-Tung County, TW;
Tsung-lung Tsai, Tai-Nan, TW;
Po-jui Liao, Taichung, TW;
Chien-ming Lai, Tainan, TW;
Ying-tsung Chen, Kaohsiung, TW;
Cheng-yu MA, Tainan, TW;
Wen-han Hung, Kaohsiung, TW;
Che-hua Hsu, Hsinchu County, TW;
Guang-Yaw Hwang, Tainan, TW;
Chun-Hsien Lin, Tainan, TW;
Hung-Ling Shih, Chiayi County, TW;
Jiunn-Hsiung Liao, Tainan, TW;
Zhi-Cheng Lee, Tainan, TW;
Shao-Hua Hsu, Taoyuan County, TW;
Yi-Wen Chen, Tainan, TW;
Cheng-Guo Chen, Changhua County, TW;
Jung-Tsung Tseng, Tainan, TW;
Chien-Ting Lin, Hsinchu, TW;
Tong-Jyun Huang, Tainan, TW;
Jie-Ning Yang, Ping-Tung County, TW;
Tsung-Lung Tsai, Tai-Nan, TW;
Po-Jui Liao, Taichung, TW;
Chien-Ming Lai, Tainan, TW;
Ying-Tsung Chen, Kaohsiung, TW;
Cheng-Yu Ma, Tainan, TW;
Wen-Han Hung, Kaohsiung, TW;
Che-Hua Hsu, Hsinchu County, TW;
UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An Oambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.